Tag: Computer Technology

IEEE Standard for Futurebus+(R), Profile M (Military): Errata, Corrections, and Clarifications

Withdrawn Jan 10, 2002. The supplement contains errata, corrections, and clarifications to IEEE Std 896.5-1993. Futurebus+ standards provide system developers with a set of tools with which high performance bus-based…

PAR WITHDRAWN 3/17/94- Standard for Small Computer Expandability Module for Futurebus+ Systems, Profile D (Desktop)

IEEE Standard for Fault Tolerant Extensions to the Futurebus+(R) Architecture

This standard is one in a family of Futurebus+TM standards. The Futurebus+ standards provide a set of tools with which to implement a bus architecture with performance and cost scalability…

Standard for Futurebus+(R) Spaceborne Systems – Profile S

In the Futurebus+® series of standards, tools with which high-performance bus-based systems may be developed are provided. This architecture provides a wide range of performance scalability over both cost and…

IEEE Standard for Radix-Independent Floating-Point Arithmetic

A family of commercially feasible ways for new systems to perform floating-point arithmetic is defined. This standard specifies constraints on parameters defining values of basic and extended floating-point numbers; add,…

Standard for Microprocessor Operating Systems Interfaces (MOSI)

IEEE Standard for Microprocessor Operating System Interfaces (MOSI)

Withdrawn Standard. Withdrawn Date: Apr 28, 1996. No longer endorsed by the IEEE. Describes the IEEE Std 855-1990, IEEE standard for microprocessor operating system interfaces (MOSI), which defines an interface…

IEEE Standard Backplane Bus Specifications for Multiprocessor Architectures: Futurebus+(R)

This document provides a level of specification sufficient to design modules that are functionally, operationally, electrically, and mechanically compatible. Additional documents are necessary only to promote a higher degree of…

IEEE Standard for Futurebus+(R) — Logical Protocol Specification

IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems.…
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