A standard syntax and semantics for VHDL register transfer level (RTL) synthesis is defined. The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with the semantics of that subset for the synthesis domain.
- Standard Committee
- C/DA - Design Automation
- Status
- Superseded Standard
- Superseded by
- 1076.6-2004
- Board Approval
- 1999-09-16
- History
-
- ANSI Approved:
- 2000-03-29
- Published:
- 2000-03-10
Working Group Details
- Society
- IEEE Computer Society
- Standard Committee
- C/DA - Design Automation
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1076.6-2004
IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
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