To develop an extension to the CTL language that provides a sufficient description of a memory-core to support the development and reuse of test and repair mechanisms for that memory after integration into SoC environment and enable creation of test patterns for the logic on the SoC external to the memory.System on Chip (SoC) test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits. This activity defines language constructs sufficient to represent the context of a memory-core and of the integration of that memory-core into an SoC, to facilitate development and reuse of test and repair mechanisms for memories. This activity also defines constructs that represent the test structures internal to the memory-core for reuse in the creation of the tests for the logic outside the memory-core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory-core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE 1450.6-2005. As a result of this extension, CTL's limitations of handling memories are addressed.
Sponsor: C/TT - Test Technology
Get Involved In The Development Of This Standard
Contact the IEEE-SA Liaison Simply click here to voice your interest. Kathryn Bennett Learn More About Standards ParticipationAnyone can participate, there are a variety of programs and services to
facilitate the involvement of industry and the public. More Become a Member and Ballot on this StandardMembership empowers you to participate & lead in the development of
standards. Tell Me More