IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.
- Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Status
- Inactive-Reserved Standard
- PAR Approval
- 2007-06-07
- Board Approval
- 2011-03-31
- History
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- ANSI Approved:
- 2012-03-27
- Published:
- 2011-06-20
- Inactivated Date:
- 2022-03-24
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Working Group
-
SCIT1581 - Static Component Interconnection Test Protocol and Architecture Working Group
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- Heiko Ehrenberg
Other Activities From This Working Group
Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.
P1581
Standard for Static Component Interconnection Test Protocol and Architecture
This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1, IEEE Standard for Test Access Port and Boundary-Scan Architecture, https://standards.ieee.org/standard/1149_1-2013.html) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.
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