P2415 - Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems
Project Details
The new standard defines the syntax and semantics for energy oriented description of hardware, software and power management for electronic systems. It enables specifying, modeling, verifying, designing, managing, testing and measuring the energy features of the device, covering both the pre- and post-silicon design flow. On the hardware side the description covers enumeration of semiconductor intellectual property components (System on Chip, board, device), memory map, bus structure, interrupt logic, clock and reset tree, operating states and points, state transitions, energy and power attributes; on the software side the description covers software activities and events, scenarios, external influences (including user input) and operational constraints; and on the power management side the description covers activity dependent energy control. The new standard is compatible with the current and future IEEE 1801 (UPF) standard to support an integrated design flow. It provides the higher level of abstraction and therefore enables earlier (more abstract) modeling of power states using UPF. Additionally, the new standard complements functional models in VHDL/Verilog/SystemVerilog/ SystemC by providing an abstraction of the design hierarchy and an abstraction of the design behavior with regard to power/energy usage.
Sponsor Committee
PAR Approval
Working Group Details
Working Group
Sponsor Committee
IEEE Program Manager