Inactive-Withdrawn Standard

IEEE 896.1-1991

IEEE Standard for Futurebus+(R) -- Logical Protocol Specification

IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.

Sponsor Committee
C/MSC - Microprocessor Standards Committee
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Status
Inactive-Withdrawn Standard
Superseding
896.1-1987
Amendment
896.1a-1993
Board Approval
1991-09-26
History
Withdrawn:
1997-12-09
ANSI Approved:
1992-04-28
Published:
1992-03-10

Working Group Details

Society
IEEE Computer Society
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Sponsor Committee
C/MSC - Microprocessor Standards Committee
Learn More About C/MSC - Microprocessor Standards Committee

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