This standard defines a vendor-neutral, unified, and extensible reference architecture for the design and description of Domain-Specific Architectures (DSAs). It specifies functional models for the organization of compute arrays, domain-specialized memory hierarchies, on-chip interconnect fabrics, and hardware-level architectural abstractions. This help improving system integration and software toolchain development in heterogeneous computing environments. By standardizing core architectural abstractions, this standard lowers the complexity of software-hardware co-design and improves system compatibility. The standard also defines a common technical benchmark and conceptual model for evaluating and comparing different DSA implementations based on their structural composition.
- Standard Committee
- CASS/DSA-SC - Domain-Specific Accelerators Standards Committee
- Status
- Active PAR
- PAR Approval
- 2026-09-25
Working Group Details
- Society
- IEEE Circuits and Systems Society
- Standard Committee
- CASS/DSA-SC - Domain-Specific Accelerators Standards Committee
- Working Group
-
DSA WG - Domain-Specific Architecture Working Group
- IEEE Program Manager
- Christian Orlando
Contact Christian Orlando - Working Group Chair
- HUI WANG
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