This Standard specifies a basic Instruction Set Architecture (ISA) for Artificial Intelligence (AI) hardware accelerators with the intent of achieving a balance between computational performance and energy efficiency. The ISA supports key industrial application scenarios, including industrial AI inference and edge AI accelerators for intelligent manufacturing, with tailored adaptations for real-time execution, computing reliability, low-power operation, and edge computing requirements. Recognizing that AI accelerators typically operate as coprocessors alongside a general-purpose host (e.g., a RISC-V core), this standard also encompasses the interface and interaction mechanisms between the accelerator and the host system. This includes standardized control protocols, memory sharing and coherence schemes, as well as interrupt handling to help ensure seamless integration and efficient collaboration. The ISA addresses the following: • computation, • logic, • control, • data transfer, and • instruction bit length. Computation instructions encompass core mathematical operations optimized for parallel execution, such as tensor multiplications, convolutions, and matrix addition. Logic instructions specify bitwise operations, masking, and conditional execution logic that enable efficient branching and precision handling for the accelerator. Control instructions include instruction sequencing, loop constructs, synchronization primitives, and the accelerator's interaction with system software. Data transfer instructions outline memory addressing modes, Direct Memory Access (DMA) mechanisms, register-to-memory instructions, and caching policies, as well as Load/Store/Move operations for matrices, vectors, and scalars. The ISA's instruction bit length details opcode formats, operand encodings, and the expansion strategies applicable to the accelerator's instruction set.
- Standard Committee
- CASS/DSA-SC - Domain-Specific Accelerators Standards Committee
- Status
- Active PAR
- PAR Approval
- 2026-03-26
Working Group Details
- Society
- IEEE Circuits and Systems Society
- Standard Committee
- CASS/DSA-SC - Domain-Specific Accelerators Standards Committee
- Working Group
-
AI-ISA WG - AI Accelerator ISA Standard Working Group
- IEEE Program Manager
- Christian Orlando
Contact Christian Orlando - Working Group Chair
- Li Du
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