This standard defines effective and efficient mechanisms to test and repair chiplet interconnects. The standard includes the following: 1. An Architecture definition for the test and repair of chiplet interconnects. The architecture consists of the following elements: chiplet interconnect clustering, cluster clocking and redundancy, cluster repair muxing and mux re-configuration support, lane numbering and repair signature format. In addition, the standard defines testing support for high volume manufacturing of chiplet interconnects. 2. A description language that defines the test and repair hardware, the signature format, message format for communication between the two dies and the die models used for validating the test infrastructure.
Working Group Details
- IEEE Computer Society
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- Sponsor Committee
- C/TT - Test Technology
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- Working Group
CITR-WG - Chiplet Interconnect Test and Repair Working Group
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- IEEE Program Manager
- Tom Thompson
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- Working Group Chair
- SREEJIT CHAKRAVARTY
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