Active Standard

IEEE 1800.2-2020

IEEE Standard for Universal Verification Methodology Language Reference Manual

The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)

Sponsor Committee
C/DA - Design Automation
Learn More About C/DA - Design Automation
Status
Active Standard
PAR Approval
2019-03-21
Superseding
1800.2-2017
Board Approval
2020-06-04
History
Published:
2020-09-14

Working Group Details

Society
IEEE Computer Society
Learn More About IEEE Computer Society
Sponsor Committee
C/DA - Design Automation
Learn More About C/DA - Design Automation
Working Group
UVM - Universal Verification Methodology Language Reference Manual
IEEE Program Manager
Vanessa Lalitte
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Working Group Chair
Justin Refice

Other Activities From This Working Group

Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.


No Active Projects

Standards approved by the IEEE SA Standards Board that are within the 10-year lifecycle.


62530-2-2023

IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual

The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.

Learn More About 62530-2-2023

These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.


1800.2-2017

IEEE Standard for Universal Verification Methodology Language Reference Manual

The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.

Learn More About 1800.2-2017

These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.


No Inactive-Withdrawn Standards

These standards are removed from active status through an administrative process for standards that have not undergone a revision process within 10 years.


No Inactive-Reserved Standards
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