Inactive-Reserved Standard

IEEE 1596-1992

IEEE Standard for Scalable Coherent Interface (SCI)

The scalable coherent interface (SCI) provides computer-bus-like services but, instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher throughput needed for high-performance multiprocessor systems. SCI supports distributed, shared memory with optional cache coherence for tightly coupled systems, and message-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bit parallel) and 1 Gb/s (serial). For applications requiring modular packaging, an interchangeable module is specified along with connector and power. The packets and protocols that implement transactions are defined and their formal specification is provided in the form of computer programs. In addition to the usual read-and-write transactions, SCI supports efficient multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and can recover from an arbitrary number of transmission failures. SCI protocols ensure forward progress despite multiprocessor conflicts (no deadlocks or starvation).

Sponsor Committee
C/MSC - Microprocessor Standards Committee
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Status
Inactive-Reserved Standard
Board Approval
1992-03-19
History
ANSI Approved:
1992-10-23
Published:
2001-05-23
Inactivated Date:
2019-11-07

Working Group Details

Society
IEEE Computer Society
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Sponsor Committee
C/MSC - Microprocessor Standards Committee
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Working Group
1596_WG - Working Group for Scalable Coherent Interface
IEEE Program Manager
Tom Thompson
Contact
Working Group Chair
David Gustavson
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