Active Standard

IEEE 1500-2022

IEEE Standard Testability Method for Embedded Core-based Integrated Circuits

A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators.

Standards Committee
C/TT - Test Technology
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Status
Active Standard
PAR Approval
2019-09-05
Superseding
1500-2005
Board Approval
2022-06-16
History
Published:
2022-10-12

Working Group Details

Society
IEEE Computer Society
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Standards Committee
C/TT - Test Technology
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Working Group
1500-2021 - C/TT/1500 Standard Testability Method for Embedded Core-based Integrated Circuits
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IEEE Program Manager
Tom Thompson
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Working Group Chair
Mike Ricchetti

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