A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators.
Working Group Details
- IEEE Computer Society
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- Sponsor Committee
- C/TT - Test Technology
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- Working Group
1500-2021 - C/TT/1500 Standard Testability Method for Embedded Core-based Integrated Circuits
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- IEEE Program Manager
- Tom Thompson
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- Working Group Chair
- Mike Ricchetti
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