Superseded Standard

IEEE 1481-2009

IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)

Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.

Standards Committee
C/DA - Design Automation
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Status
Superseded Standard
PAR Approval
2002-08-15
Superseded by
1481-2019
Superseding
1481-1999
Board Approval
2009-12-09
History
ANSI Approved:
2010-05-21
Published:
2010-03-11

Working Group Details

Society
IEEE Computer Society
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Standards Committee
C/DA - Design Automation
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Working Group
WG1481R - Integrated Circuit (IC) Open Library Architecture (OLA) Working Group
IEEE Program Manager
Vanessa Lalitte
Contact
Working Group Chair
Stanley Krolikoski

Other Activities From This Working Group

Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.


No Active Projects

Standards approved by the IEEE SA Standards Board that are within the 10-year lifecycle.


1481-2019

IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA)

Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, the means by which EDA vendors can meet their application performance and capacity needs are discussed.

Learn More

These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.


1481-1999

IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System

Ways for integrated circuit designers to analyze chip timing and power consistently across a broad set of electric design automation (EDA) applications are covered in this standard. Methods by which integrated circuit vendors can express timing and power information once per given technology are also covered. In addition, this standard covers means by which EDA vendors can meet their application performance and capacity needs.

Learn More

These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.


No Inactive-Withdrawn Standards

These standards are removed from active status through an administrative process for standards that have not undergone a revision process within 10 years.


No Inactive-Reserved Standards
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