The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language. (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).
- Sponsor Committee
- C/DA - Design Automation
Learn More About C/DA - Design Automation - Status
- Superseded Standard
- PAR Approval
- 2004-08-12
- Superseding
- 1800-2009
- Board Approval
- 2005-11-08
- History
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- ANSI Approved:
- 2006-11-02
- Published:
- 2006-04-07
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/DA - Design Automation
Learn More About C/DA - Design Automation - Working Group
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VLOGSyn - Verilog Register Transfer Level Synthesis Working Group
- IEEE Program Manager
- Vanessa Lalitte
Contact Vanessa Lalitte - Working Group Chair
- Michael Mcnamara
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1364.1-2002
IEEE Standard for Verilog Register Transfer Level Synthesis
Superseded by IEC/IEEE 62142-2005. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. To define syntax and semantics which can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation tools currently use the IEEE 1364 standard. This will allow users of synthesis tools to produce well-defined designs whose functional characteristics are independent of any particular synthesis implementation by making their design compliant with this developed standard. Standard syntax and semantics for Verilog u00ae HDL-based RTL synthesis are described inthis standard.
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