Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1™ to describe and operate the on-chip circuits.
- Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Status
- Active Standard
- PAR Approval
- 2013-10-21
- Board Approval
- 2017-05-18
- History
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- ANSI Approved:
- 2018-11-26
- Published:
- 2017-07-28
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Working Group
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HJTAG - High Speed Test Access Port and On-chip Distribution Architecture
Learn More About HJTAG - High Speed Test Access Port and On-chip Distribution Architecture - IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- Mike Ricchetti
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