Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1™ to describe and operate the on-chip circuits.
Working Group Details
- IEEE Computer Society
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- Sponsor Committee
- C/TT - Test Technology
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- Working Group
HJTAG - High Speed Test Access Port and On-chip Distribution Architecture
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- IEEE Program Manager
- Tom Thompson
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- Working Group Chair
- Mike Ricchetti
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