This standard defines test logic that can be included in an integrated circuit (IC), as well as structural and procedural description languages, to provide standardized approaches to - testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board (PCB) or other substrate; - testing the integrated circuit itself; and - observing, modifying, or loading data inside an integrated circuit during test, programming, configuration, or debug of the integrated circuit or the circuitry connected to the component.
- Standard Committee
- C/TT - Test Technology
- Status
- Active PAR
- PAR Approval
- 2022-06-16
- Superseding
- 1149.1-2013
Working Group Details
- Society
- IEEE Computer Society
- Standard Committee
- C/TT - Test Technology
- Working Group
-
Boundary Scan Architecture - Standard Test Access and Boundary Scan Architecture WG P1149.1
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- Heiko Ehrenberg
Other Activities From This Working Group
Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.
No Active Projects
Standards approved by the IEEE SA Standards Board that are within the 10-year lifecycle.
No Active Standards
These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.
No Superseded Standards
These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.
No Inactive-Withdrawn Standards
These standards are removed from active status through an administrative process for standards that have not undergone a revision process within 10 years.
1149.1-2013
IEEE Standard for Test Access Port and Boundary-Scan Architecture
Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards. Also, a language is defined that allows rigorous structural description of the component-specific aspects of such testability features, and a second language is defined that allows rigorous procedural description of how the testability features may be used.
1149.8.1-2012
IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and/or Active Components
Extensions to IEEE Std 1149.1 that define the boundary-scan structures and methods required to facilitate boundary-scan-based stimulus of interconnections to passive and/or active components are specified. Such networks are not adequately addressed by existing standards, including those networks that are ac-coupled or differential. The selective ac stimulus generation enabled by this standard, when combined with non-contact signal sensing, will allow testing of the connections between devices adhering to this standard and circuit elements such as series components, sockets, connectors, and integrated circuits (ICs) that do not implement IEEE Std 1149.1. This standard also specifies Boundary-Scan Description Language (BSDL) extensions to IEEE Std 1149.1 required to describe and support the new structures and methods.