The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.
Working Group Details
- IEEE Computer Society
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- Sponsor Committee
- C/DA - Design Automation
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- Working Group
VITAL_WG - VITAL Application Specific Integrated Circuit Working Group
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- IEEE Program Manager
- Vanessa Lalitte
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- Working Group Chair
- Ajayharsh Varikat
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