Superseded Standard

IEEE 1076.1.1-2004

IEEE Standard VHDL Analog and Mixed-Signal Extensions---Packages for Multiple Energy Domain Support

This standard defines a collection of VHDL 1076.1 packages, compatible with IEEE Std 1076.1TM-1999, along with recommendations for conforming use, in order to facilitate the interchange of simulation models of physical components and subsystems. The packages include the definition of standard types, subtypes, natures, and constants for modeling in multiple energy domains (electrical, fluidic, mechanical, etc.).

Sponsor Committee
C/DA - Design Automation
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Status
Superseded Standard
PAR Approval
2002-05-09
Superseded by
1076.1.1-2011
Board Approval
2004-12-16
History
ANSI Approved:
2005-04-05
Published:
2005-06-17

Working Group Details

Society
IEEE Computer Society
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Sponsor Committee
C/DA - Design Automation
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Working Group
StdPkg_WG - Standards Packages Working Group
IEEE Program Manager
Vanessa Lalitte
Contact
Working Group Chair
Homer Alan Mantooth
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No Active Standards

1076.2-1996

IEEE Standard VHDL Mathematical Packages

The MATH_REAL package declaration, the MATH_COMPLEX package declaration, and the semantics of the standard mathematical definition and conventional meaning of the functions that are part of this standard are provided. Ways for users to implement this standard are given in an informative annex. Samples of the MATH_REAL and MATH_COMPLEX package bodies are provided in an informative annex on diskette as guidelines for implementors to verify their implementation of this standard. Implementors may choose to implement the package bodies in the most efficient manner available to them. The standard package bodies (subclauses B.1 and B.2) are available for free download at: http://standards.ieee.org/downloads/1076/1076.2-1996/

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1076.3-1997

IEEE Standard VHDL Synthesis Packages

The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.

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