A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.(The PDF of this standard is available to you at no cost thru the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page)
- Standard Committee
- C/DA - Design Automation
- Status
- Superseded Standard
- PAR Approval
- 2016-05-12
- Superseded by
- 1801-2024
- Superseding
- 1801-2015
- Board Approval
- 2018-09-27
- History
-
- Published:
- 2019-03-29
Working Group Details
- Society
- IEEE Computer Society
- Standard Committee
- C/DA - Design Automation
- Working Group
-
UPF - UPF: Standard for Design and Verification of Low Power Integrated Circuits
- IEEE Program Manager
- Vanessa Lalitte
Contact Vanessa Lalitte - Working Group Chair
- john Decker
Other Activities From This Working Group
Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.
No Active Projects
Standards approved by the IEEE SA Standards Board that are within the 10-year lifecycle.
1801-2024
IEEE Draft Standard for Design and Verification of Low Power, Energy Aware Electronic Systems
Significant community acceptance and environmental compatibility items to be considered during the planning and design phases, the construction period, and the operation of electric supply substations are identified, and ways to address these concerns to obtain community acceptance and environmental compatibility are documented. On-site generation and telecommunication facilities are not considered.
61523-4-2023
IEEE/IEC International Standard--Delay and power calculation standards--Part 4: Design and Verification of Low-Power, Energy-Aware Electronic Systems
A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power-management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.
These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.
1801-2009
IEEE Standard for Design and Verification of Low Power Integrated Circuits
The power supplied to elements in an electronic design affects the way circuits operate. Although this is obvious when stated, today's set of high-level design languages have not had a consistent way to concisely represent the regions of a design with different power provisions, nor the states of those regions or domains. This standard provides an HDL-independent way of annotating a design with power intent. In addition, the level-shifting and isolation between power domains may be described for a specific implementation, from high-level constraints to particular configurations. When the logic in a power domain receives different power supply levels, the logic state of portions of the design may be preserved with various state-retention strategies. This standard provides mechanisms for the refined and specific description of intent, effect, and implementation of various retention strategies. Incorporating components into designs is greatly assisted by the encapsulation and specification of the characteristics of the power environment of the design and the power requirements and capabilities of the components; this information encapsulation mechanism is also described in this standard. The analysis of the various power modes of a design is enabled with a combination of the description of the power modes and the collection, generation, and propagation of switching information.
1801-2013
IEEE Standard for Design and Verification of Low-Power Integrated Circuits
A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit https://ieeexplore.ieee.org/browse/standards/get-program/page for more details.)
1801-2015
IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems
A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power-intent specifications required for IP-based design flows.
1801a-2014
IEEE Standard for Design and Verification of Low-Power Integrated Circuits--Amendment 1
The set of changes required to address technical and editorial errors that have been identified in IEEE Std 1801-2013 are specified in this amendment. In addition this amendment also specifies a few changes and enhancements to remove some ambiguities and inconsistencies related to the semantics of power states, power supplies, precedence rules, and location of power management cells.
These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.
No Inactive-Withdrawn Standards
These standards are removed from active status through an administrative process for standards that have not undergone a revision process within 10 years.
No Inactive-Reserved Standards