Working Group Details
System Level Power Modeling - Power Modeling: Standard for Enabling System Level Analysis
|Working Group Chair||
|IEEE Program Manager|
This standard describes a parameterized and abstracted power model enabling system, software, and hardware intellectual property (IP)-centric power analysis and optimization. It defines concepts for the development of parameterized, accurate, efficient, and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage, and temperature (PVT) independence; power and thermal management interface; and workload and architecture parameterization. Such models are suitable for use in software development flows and hardware design flows, as well as for representing both pre-silicon-estimated and post-silicon-measured data. This standard also defines the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models to help guide development and usage of other related power, workload, and functional modeling standards, such as UPF IEEE Std 1801(TM)-2018, SystemC IEEE Std 1666(TM)-2016, and SystemVerilog IEEE Std 1800(TM)-2017. Beyond defining the concepts and related standard requirements, this standard also recommends the use of other relevant design flow standards (e.g., IP-XACT IEEE Std 1685(TM)-2014 [B2]2), with the objective of enabling more complete and usable power-aware design flows.