This standard leverages existing standards-based test access mechanisms to capture and retrieve flip-flop and array/memory states. This standard defines a methodology for scan and memory/array debug data extraction for effective functional debug of System-on-Chip (SoC) and addresses other essential architectural modifications needed to support this, such as power-management changes. This standard provides a reliable and consistent methodology on trigger-based freezing of SoC scan and array states, and retrieval of those states.