This standard specifies embeddable and encapsulating markup syntaxes for design intellectual property encryption and rights management, together with recommendations for integration with design specification formats described in IEEE 1800 (SystemVerilog) and IEEE 1076 (VHDL). It also recommends use models for interoperable tool and hardware flows, which will include selecting encryption and encoding algorithms and encryption key management. The recommendation includes a description of the trust model assumed in the recommended use models. This standard does not specifically include any consideration of digitally encoded entertainment media. In the context of this document, the term IP will be used to mean electronic design intellectual property. Electronic design intellectual property is a term used in the electronic design community. It refers to a reusable collection of design specifications that represent the behavior, properties, and/or representation of the design in various media. Examples of these collections include, but are not limited to, the following: A unit of electronic system design; A design verification and analysis scheme (e.g., test bench); A netlist indicating elements and the interconnection thereeof to implement a function; A set of fabrication instructions; A physical layout design or chip layout; A design intent specification The term is partially derived from the common practice for the collection to be considered the intellectual property of one party. Hardware and software descriptions are encompassed by this term.