IEEE P1500 - IEEE Draft Standard Testability Method for Embedded Core-based Integrated Circuits
Project Details
This standard defines a mechanism for the test of core designs within a system on chip (SoC). This mechanism constitutes a hardware architecture and leverages the core test language (CTL) to facilitate communication between core designers and core integrators.
Standards Committee
PAR Approval
PARs
Additional Resources Details
Historical Base Standard
Working Group Details
Working Group
Standards Committee
Society
IEEE Program Manager