P1450.1 - Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Semiconductor Design Environments
Project Details
Define structures in STIL to support usage as semiconductor simulation stimulus; including: 1) mapping signal names to equivalent design references, 2) interface between Scan and Built-In Self-Test (BIST), and the logic simulation, 3) data types to represent unresolved states in a pattern, 4) parallel or asynchronous pattern execution on different design blocks, and 5) expression-based conditional execution of pattern constructs. Define structures in STIL to support the definition of test patterns for sub-blocks of a design (i.e., embedded cores) such that these tests can be incorporated into a complete higher-level device test. Define structures in STIL to relate fail information from device testing environments back to original stimulus and design data elements.
Standards Committee
PAR Approval
Additional Resources Details
Historical Base Standard
Working Group Details
Working Group
Standards Committee
IEEE Program Manager