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2427 - Standard for Analog Defect Modeling and Coverage

The primary purpose of this standard is to allow people to communicate information about defect coverage in a way that allows assessment of test and circuit quality as well as prediction of important metrics (simulation time, DfT circuit area, test time, test escapes, etc.). Given a circuit description and a test pattern, this standard defines how to enumerate the universe of defects, determine which defects are detected by the test pattern, and report the coverage results. By defining analog test coverage, this standard is useful for several other purposes. First, this standard guides efficient simulation of defects to ensure that the defect models achieve a desirable trade-off between cost-effective simulation times and accurate modeling of behavior seen in real circuits. Second, this standard facilitates estimation of test escape rates (historically measured in defective parts per million -- DPPM) to facilitate trade-offs between cost of test, time to market, and quality. The portion of all potential defects that tests must detect in a circuit will depend on the likelihood of the defects occurring, the consequences of undetected defects in the intended application for the IC, and the likelihood that a defect that occurs has a significant consequence. Third, this standard facilitates improvements in design for test (DfT) and test generation methods. Many DfT and test techniques, including built-in self-test (BIST), have been developed which, despite cost advantages, are not used in practice because their impact on defect coverage is questioned due to the lack of a well-understood and silicon-corroborated analog defect model. By allowing reliable comparisons of DfT and test techniques, this standard facilitates automation and quality improvements.
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