Digital circuits have various structural representations either in high level hardware description languages (HDLs) which can then be synthesised or in netlist forms. Commercial tools for automatic test pattern generation (ATPG) using algorithmic techniques today operate on a structural netlist of the design under test (DUT). The test quality signoff process mandatorily includes a minimal coverage requirement, to be obtained using these tool generated patterns on the DUT. This motivates the need for standard processes for (i) counting faults across different fault models, (ii) classifying these faults, and (iii) reporting the coverage, across different ATPG tools which are used to generate test patterns for these digital circuits. Such standard processes will make test qualification based on ATPG generated patterns and fault coverage metrics easier and independent of the ATPG tool used. A uniform fault coverage and pattern count based metric can now be generated for large chips with complex functionality which is being integrated into system-on-chips (SOCs) with a heterogeneous mix of modules therein, often consisting of Building Blocks (such as Intellectual Property (IP) cores - which are often sourced from design teams different from those designing the chips themselves), test patterns for which can be generated using different ATPG tools. (As the first step, only the classical stuck-at 0 and stuck-at 1 fault model will be considered. The fault accounting, classification and coverage reporting standard will be extended to cover other fault models subsequently).The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it will be incumbent on all ATPG tools (which comply to this standard) to report fault coverage in a uniform way, thereby facilitating the generation of a uniform coverage (and hence a test quality) metric for large chips with different cores and modules, for which test patterns have been independently generated.
Sponsor: C/TT - Test Technology
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