A two-level code construction scheme for non-volatile memories (NVM) that is based on low-density parity-check codes is specified in this standard. This scheme constructs an auxiliary codeword that encodes a subset of bits from the primary packets stored in an NVM memory unit. The auxiliary codeword is decoded only when the detection of at least one of the primary codewords fails. The encoding and decoding techniques for this scheme are presented. The two-level scheme outperforms the traditional one-level method while it requires only a small memory overhead and negligible latency. Moreover, it outperforms the one-level scheme that uses a code that is twice as long in the low raw bit error rate regime.
- Sponsor Committee
- C/MSC - Microprocessor Standards Committee
Learn More About C/MSC - Microprocessor Standards Committee - Status
- Active Standard
- PAR Approval
- 2013-05-10
- Board Approval
- 2018-09-27
- History
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- Published:
- 2019-02-28
Additional Resources
- Erratas
- 1890-2018_errata.pdf
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/MSC - Microprocessor Standards Committee
Learn More About C/MSC - Microprocessor Standards Committee - Working Group
-
ECC_NVM_P1890 WG - Error Correction Coding for Non-Volatile Memories_P1890 WG
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- Kiran Gunnam
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