UPF - UPF: Standard for Design and Verification of Low Power Integrated Circuits

John Biggs

This standard defines the syntax and semantics of a format used to express power intent in energy aware electronic system design. Power intent includes the concepts and information required for specification and validation, implementation and verification, and modelling and analysis of power managed electronic systems. This standard also defines the relationship between the power intent captured in this format and design intent captured via other formats (e.g., standard hardware description languages and cell libraries).

The power supplied to elements in an electronic design affects the way circuits operate. Although this is obvious when stated, today?s set of high-level design languages have not had a consistent way to concisely represent the regions of a design with different power provisions, nor the states of those regions or domains. This standard provides an HDL-independent way of annotating a design with power intent. In addition, the level-shifting and isolation between power domains may be described for a specific implementation, from high-level constraints to particular configurations. When the logic in a power domain receives different power supply levels, the logic state of portions of the design may be preserved with various state-retention strategies. This standard provides mechanisms for the refined and specific description of intent, effect, and implementation of various retention strategies. Incorporating components into designs is greatly assisted by the encapsulation and specification of the characteristics of the power environment of the design and the power requirements and capabilities of the components; this information encapsulation mechanism is also described in this standard. The analysis of the various power modes of a design is enabled with a combination of the description of the power modes and the collection, generation, and propagation of switching information.

A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit https://ieeexplore.ieee.org/browse/standards/get-program/page for more details.)

The set of changes required to address technical and editorial errors that have been identified in IEEE Std 1801-2013 are specified in this amendment. In addition this amendment also specifies a few changes and enhancements to remove some ambiguities and inconsistencies related to the semantics of power states, power supplies, precedence rules, and location of power management cells.

A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.(The PDF of this standard is available to you at no cost thru the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page)