Standard Details
The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.
| Standards Committee | |
| Status |
Active
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| Board Approval |
2020-06-04
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| History |
Published Date:2020-09-14
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Additional Resources Details
| PAR |
Working Group Details
| Working Group |
UVM - Universal Verification Methodology Language Reference Manual
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| Working Group Chair |
Justin Refice
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| Standards Committee | |
| Society | |
| IEEE Program Manager | |
| Existing Standards |
The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the GET IEEE program https://ieeexplore.ieee.org/browse/standards/get-program/page)
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