IEEE 1800.2-2020 - IEEE Standard for Universal Verification Methodology Language Reference Manual

Standard

Active

Standard Details

The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the IEEE GET program https://ieeexplore.ieee.org/browse/standards/get-program/page/series?id=80)

Sponsor Committee	C/DA - Design Automation
Status	Active
Board Approval	2020-06-04
History	Published Date:2020-09-14

Additional Resources Details

Pars	Approved PAR

Working Group Details

Working Group	UVM - Universal Verification Methodology Language Reference Manual
Working Group Chair	Justin Refice
Sponsor Committee	C/DA - Design Automation
Society	IEEE Computer Society
IEEE Program Manager	Vanessa Lalitte
Existing Standards	Superseded IEEE 1800.2-2017 - IEEE Standard for Universal Verification Methodology Language Reference Manual The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library.