This document specifies a standard for use of very high-speed integrated circuit hardware
description language (VHDL) to model synthesizable register-transfer level digital logic. A
standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of
the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs
are identified that should be ignored or flagged as errors.