Project Details
This standard defines a data format with which results of functional safety analyses (such as FMEA (Failure Mode and Effects Analysis), FMEDA (Failure Modes, Effects and Diagnostic Analysis), FMECA (Failure Mode, Effects and Criticality analysis), FTA (Fault Tree analysis) and related functional safety verification activities - such as fault injection - executed for IPs (Intellectual Property. See note in section 8.1), SoCs (System on Chip) and mixed signal ICs (Integrated Circuit) can be exchanged and made available to system integrators. The format will define languages, data fields and parameters with which the result of those analyses and verification activities can be represented, in a technology independent way. The goal of the standard is to provide a common ground for EDA (Electronic Design Automation), SoC and IP vendors in needs of developing tools, SoC and IP for functional safety critical applications.
Standards Committee | |
PAR Approval |
2019-11-07
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PARs |
Working Group Details
Working Group |
Functional Safety Format - Exchange/Interoperability format for functional safety analysis and safety verification of IP, SoC and mixed signal ICs
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Standards Committee | |
Society | |
IEEE Program Manager |