This standard defines a data bus used by chiplet interfaces including interface requirements, physical packaging requirements, and testability requirements. The standard also encompasses application scenarios, an architecture, an adapter layer, and a physical layer. Additionally, implications for the bus's protocol layer, and link layer, are covered. This standard specifies a super/enhanced PHY composed of an adapter layer bridging differences in different PHY layers from existing standards, and a PHY layer accommodating diverse working frequencies and bit widths encountered across existing standards.
- Sponsor Committee
- CASS/IC-SC - Integrated Circuit Design and Test for Emerging Circuits and Systems Standards Committee
- Status
- Active PAR
- PAR Approval
- 2024-03-21
Working Group Details
- Society
- IEEE Circuits and Systems Society
Learn More About IEEE Circuits and Systems Society - Sponsor Committee
- CASS/IC-SC - Integrated Circuit Design and Test for Emerging Circuits and Systems Standards Committee
- Working Group
-
CICWG - Chiplet Interface Circuit
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- qinfen hao
Other Activities From This Working Group
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