This standard defines effective and efficient mechanisms to test and repair chiplet interconnects. The standard includes the following: 1. An Architecture definition for the test and repair of chiplet interconnects. The architecture consists of the following elements: chiplet interconnect clustering, cluster clocking and redundancy, cluster repair muxing and mux re-configuration support, lane numbering and repair signature format. In addition, the standard defines testing support for high volume manufacturing of chiplet interconnects. 2. A description language that defines the test and repair hardware, the signature format, message format for communication between the two dies and the die models used for validating the test infrastructure.
- Standard Committee
- C/TT - Test Technology
- Status
- Active PAR
- PAR Approval
- 2023-09-21
Working Group Details
- Society
- IEEE Computer Society
- Standard Committee
- C/TT - Test Technology
- Working Group
-
CITR-WG - Chiplet Interconnect Test and Repair Working Group
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- SREEJIT CHAKRAVARTY
Other Activities From This Working Group
Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.
No Active Projects
Standards approved by the IEEE SA Standards Board that are within the 10-year lifecycle.
No Active Standards
These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.
No Superseded Standards
These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.
No Inactive-Withdrawn Standards
These standards are removed from active status through an administrative process for standards that have not undergone a revision process within 10 years.
No Inactive-Reserved Standards