This standard defines the hardware and software architecture of hybrid quantum-classical computing environments. It specifies the interconnection between one or more quantum processor units (QPUs) and one or more central processing units (CPUs) and/or graphics processing units (GPUs) and/or tensor processing units (TPUs) and/or field programmable gate arrays (FPGAs). This standard includes the definition of application programming interfaces (APIs) to improve high-performance computing (HPC) and excludes any definition of classical (super) computers and quantum computers.
- Sponsor Committee
- C/SABSC - Standards Activities Board Standards Committee
Learn More About C/SABSC - Standards Activities Board Standards Committee - Status
- Active PAR
- PAR Approval
- 2022-09-21
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/SABSC - Standards Activities Board Standards Committee
Learn More About C/SABSC - Standards Activities Board Standards Committee - Working Group
-
QuCLC - Hybrid Quantum-Classical Computing Working Group
- IEEE Program Manager
- Jonathan Goldberg
Contact Jonathan Goldberg - Working Group Chair
- Gilles CEYSSAT
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