IEEE Std 1838 is a die-centric standard; it applies to a die that is intended to be part of a multi-die stack. This standard defines die-level features that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks in both pre-packaging, post-packaging, and board-level situations. The primary focus of inter-die interconnect technology addressed by this standard is through-silicon vias (TSVs); however, this does not preclude its use with other interconnect technologies such as wire-bonding
- Standard Committee
- C/TT - Test Technology
- Status
- Active Standard
- PAR Approval
- 2011-02-02
- Proposed Amendment
-
P1838a
- Board Approval
- 2019-11-07
- History
-
- Published:
- 2020-03-13
Working Group Details
- Society
- IEEE Computer Society
- Standard Committee
- C/TT - Test Technology
- Working Group
-
3DT-WG - 3D-Test Working Group
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- Adam Cron
Other Activities From This Working Group
Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.
P1838a
IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits Amendment 1: Testing of Interconnects External to Multi-Die Assemblies using Boundary-Scan Register (BSR) Segments
This amendment specifies a methodology and language descriptions which enable testing of external interconnects for multi-die assemblies (e.g., 2D/2.5D packages), where the dies in the assembly comply to IEEE Std 1838 and one or more of the dies contain Boundary-Scan Register (BSR) segments compliant to IEEE Std 1149.1. The methodology does not address multi-die assembly configurations where only one die has BSR segments and that die is the first die of the 1838 assembly configuration. In this case, the requirements of IEEE Std 1149.1 apply on the multi-die assembly. The languages describe the following: • The mapping of the external interconnect IOs to the BSRs • Any hierarchical connections between the dies required to access the BSRs • Procedures to initialize the multi-die assembly such that boundary-scan testing of the external interconnects can be performed (pre-amble), and to return the multi-die assembly back to a reset state (post-amble).
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