A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators.
- Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Status
- Active Standard
- PAR Approval
- 2019-09-05
- Superseding
- 1500-2005
- Board Approval
- 2022-06-16
- History
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- Published:
- 2022-10-12
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Working Group
-
1500-2021 - C/TT/1500 Standard Testability Method for Embedded Core-based Integrated Circuits
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- Mike Ricchetti
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