Reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits is required for system-on-chip (SoC) tests. This standard defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an SoC. This facilitates the development and reuse of test and repair mechanisms for memories. This standard also defines constructs that represent the test structures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6(TM)-2005. As a result of this extension, CTL's limitations of handling memories are addressed.
- Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Status
- Active Standard
- PAR Approval
- 2007-05-07
- Board Approval
- 2014-03-27
- History
-
- Published:
- 2014-06-13
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/TT - Test Technology
Learn More About C/TT - Test Technology - Working Group
-
1450.6.2WG - Working Group for Core Test Language (CTL)
- IEEE Program Manager
- Tom Thompson
Contact Tom Thompson - Working Group Chair
- Saman Adham
Other Activities From This Working Group
Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.
P1450.6.2
Standard for Memory Modeling in Core Test Language
System on Chip (SoC) test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits. This standard defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an SoC. This facilitates the development and reuse of test and repair mechanisms for memories. This standard also defines constructs that represent the test structures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6(TM)-2005. As a result of this extension, CTL's limitations of handling memories are addressed.
Standards approved by the IEEE SA Standards Board that are within the 10-year lifecycle.
No Active Standards
These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.
No Superseded Standards
These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.
No Inactive-Withdrawn Standards
These standards are removed from active status through an administrative process for standards that have not undergone a revision process within 10 years.
No Inactive-Reserved Standards