The VITAL (VHDL Initiative Towards ASIC Libraries)ASIC Modeling Specification is defined in this standard.This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit)components in VHDL.
- Sponsor Committee
- C/DA - Design Automation
Learn More About C/DA - Design Automation - Status
- Inactive-Withdrawn Standard
- PAR Approval
- 1999-06-26
- Superseding
- 1076.4-1995
- Board Approval
- 2000-09-21
- History
-
- Withdrawn:
- 2009-01-26
- ANSI Approved:
- 2001-02-01
- Published:
- 2001-09-28
Working Group Details
- Society
- IEEE Computer Society
Learn More About IEEE Computer Society - Sponsor Committee
- C/DA - Design Automation
Learn More About C/DA - Design Automation - Working Group
-
VITAL_WG - VITAL Application Specific Integrated Circuit Working Group
- IEEE Program Manager
- Vanessa Lalitte
Contact Vanessa Lalitte - Working Group Chair
- Ajayharsh Varikat
Other Activities From This Working Group
Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.
No Active Projects
Standards approved by the IEEE SA Standards Board that are within the 10-year lifecycle.
No Active Standards
These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.
No Superseded Standards
These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.
No Inactive-Withdrawn Standards
These standards are removed from active status through an administrative process for standards that have not undergone a revision process within 10 years.
No Inactive-Reserved Standards