This standard supports the ability to develop accurate, efficient, and interoperable power models for complex designs, to be used with a variety of commercial products throughout an electronic system design, analysis, and verification flows.This standard proposes a meta-model / meta-standard focused on parameterization and abstraction, enabling system, software and hardware IP-centric power analysis and optimization. This standard defines concepts for the development of parameterized, accurate, efficient and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage and temperature (PVT) independence, power and thermal management interface, workload and architecture parameterization. Such models are suitable for use in software development flows and hardware design flows, as well as representing both pre-silicon estimated and post-silicon measured data. This standard also defines the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models, to help guide development and usage of other related power, workload and functional modeling standards, such as UPF IEEE Std-P1801, SystemC IEEE Std- 1666, SystemVerilog IEEE Std-1800, and possibly others. Beyond defining the concepts and related standard requirements, the proposed specification recommends the use of other relevant design flow standards (e.g. IP-XACT) with the objective of enabling more complete and usable power-aware design flows.
Get Involved In The Development Of This Standard
Contact the IEEE-SA Liaison Simply click here to voice your interest. Jonathan Goldberg Learn More About Standards ParticipationAnyone can participate, there are a variety of programs and services to
facilitate the involvement of industry and the public. More Become a Member and Ballot on this StandardMembership empowers you to participate & lead in the development of
standards. Tell Me More