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P1838 - Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

For 3D-SICs, three parties are involved: Die Maker(s), Stack Maker(s), and Stack User(s). All circuit features of the stack are included in the individual die designs. Design and integration of test access features needs to be done by the Die Maker(s), not only to serve their own (pre-stacking) test objectives, but also to serve test objectives of Stack Maker and Stack User. After stacking, test (control and data) signals need to be able to travel from the stack's external I/Os up and down through the stack. Hence, the test access features in the various dies of the stack need to function in a concerted and interoperable fashion. Different dies might have their own technologies, design set-up, and test and design-for-test approaches; the standard should not modify those. The standard defines test access features for a die that enable the transportation of test stimuli and responses both for testing THIS DIE and its inter-die connections, as well as for testing OTHER DIES in the stack and their inter-die connections.The proposed standard is a 'die-centric' standard; it applies to a die that is intended to be part of a multi-die stack. The proposed standard defines die-level features, that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks in both pre-packaging, post-packaging, and board-level situations. The primary focus of inter-die interconnect technology addressed by this standard is Through-Silicon Vias (TSVs); however, this does not preclude its use with other interconnect technologies such as wire-bonding. The standard will consist of two related items. 1. 3D Test Wrapper Hardware On-die hardware features that enable transportation of test (control and data) signals in the following configurations. * Pre-stacking: From on-die I/Os to die-internal DfT/test features, and vice versa. These on-die I/Os might be functional I/Os; however, if they are not present or not accessible, it might be necessary to add additional test I/Os. * Post-stacking o 'Turn' mode: From on-die I/Os to die-internal DfT/test features, and vice versa. These on-die I/Os might be external I/Os on the die itself, and/or inter-die interconnections coming from (or going to) an adjacent die in the stack. o 'Elevator' mode: From on-die I/Os, through THIS DIE, to the inter-die interconnections to an adjacent die, and vice versa. These on-die I/Os might be external I/Os on the die itself and/or inter-die interconnections coming from (or going to) another adjacent die in the stack. 2. Description + Description Language A description of the Test Wrapper features in a standardized human- and computer-readable language. This description should allow the usage of the die within a multi-die stack for test and test access purposes. The proposed standard does not mandate specific defect or fault models, test generation methods, nor die-internal design-for-test, but instead focuses on generic test access to and between dies in a multi-die stack. The proposed standard is based on and works with digital scan-based test access and should leverage existing test access ports (such as based on IEEE Std 1149.x) and on-chip design-for-test (such as IEEE Std 1500) and design-for-debug (IEEE P1687) infrastructure wherever applicable and appropriate. The proposed standard is 'die-centric', and hence does not aim at 'stack/product-centric' challenges, solutions, and standards, such as the inclusion of Boundary Scan features for board-level interconnect testing. However, the proposed standard should not prohibit the application of such solutions.
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