IEEE 62142-2005 - IEC 62142 Ed. 1 (IEEE Std 1364.1(TM)-2002): Standard for Verilog(R) Register Transfer Level Synthesis
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Replaces IEEE Std 1364.1-2002/ Dual logo standard To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.
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