A methodology for accessing instrumentation embedded within a semiconductor device, without defining the instruments or their features themselves, via the IEEE 1149.1(TM) test access port (TAP) and/or other signals, is described in this standard. The elements of the methodology include a hardware architecture for the on-chip network connecting the instruments to the chip pins, a hardware description language to describe this network, and a software language and protocol for communicating with the instruments via this network.
Working Group Details
Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device
This standard defines a methodology for access to and operation of embedded instrumentation, without defining the instruments or their features themselves, via one or more well-specified digital interfaces. Some of these interfaces are suitable to be hosted under the IEEE 1149.1 Test Access Port (TAP). The principal elements of the standard are the access architecture and two description language components: one is for describing the connectivity of the instruments, the network containing them, and the behavior of their interfaces to this network; the other is for describing the communication and interaction with the instruments.