62530-2007 - IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
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This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI). This standard enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.
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