Aspects of fault models as they are relevant to the generation of test patterns for digital circuits are formalized in this standard. Fault counting, fault classification, and fault coverage reporting across different automatic test pattern generation (ATPG) tools, for the single stuck-at fault model are included in the scope. It shall be incumbent for fault coverage to be reported in a uniform way on all ATPG tools (that comply with this standard). The generation of a uniform coverage (and, hence, a uniform test quality) metric for large chips [including systems-on-chips (SOCs)] with different cores and modules for which test patterns have been independently generated will be facilitated by this standard.