Superseded Standard

IEEE 1076.2-1996

IEEE Standard VHDL Mathematical Packages

The MATH_REAL package declaration, the MATH_COMPLEX package declaration, and the semantics of the standard mathematical definition and conventional meaning of the functions that are part of this standard are provided. Ways for users to implement this standard are given in an informative annex. Samples of the MATH_REAL and MATH_COMPLEX package bodies are provided in an informative annex on diskette as guidelines for implementors to verify their implementation of this standard. Implementors may choose to implement the package bodies in the most efficient manner available to them. The standard package bodies (subclauses B.1 and B.2) are available for free download at: http://standards.ieee.org/downloads/1076/1076.2-1996/

Sponsor Committee
C/DA - Design Automation
Learn More About C/DA - Design Automation
Status
Superseded Standard
Board Approval
1996-09-19
History
ANSI Approved:
1997-03-14
Published:
1996-11-30
Reaffirmed:
2002-12-11

Additional Resources

Downloads
1076.2-1996_downloads.zip

Working Group Details

Society
IEEE Computer Society
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Sponsor Committee
C/DA - Design Automation
Learn More About C/DA - Design Automation
Working Group
StdPkg_WG - Standards Packages Working Group
IEEE Program Manager
Vanessa Lalitte
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Working Group Chair
Homer Alan Mantooth

Other Activities From This Working Group

Current projects that have been authorized by the IEEE SA Standards Board to develop a standard.


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These standards have been replaced with a revised version of the standard, or by a compilation of the original active standard and all its existing amendments, corrigenda, and errata.


1076.1.1-2004

IEEE Standard VHDL Analog and Mixed-Signal Extensions---Packages for Multiple Energy Domain Support

This standard defines a collection of VHDL 1076.1 packages, compatible with IEEE Std 1076.1TM-1999, along with recommendations for conforming use, in order to facilitate the interchange of simulation models of physical components and subsystems. The packages include the definition of standard types, subtypes, natures, and constants for modeling in multiple energy domains (electrical, fluidic, mechanical, etc.).

Learn More About 1076.1.1-2004

1076.3-1997

IEEE Standard VHDL Synthesis Packages

The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.

Learn More About 1076.3-1997

These standards have been removed from active status through a ballot where the standard is made inactive as a consensus decision of a balloting group.


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