This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.
Working Group Details
- IEEE Computer Society
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- Sponsor Committee
- C/DA - Design Automation
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- Working Group
SI-WG - VHDL Register Transfer Level (RTL) Synthesis Working Group
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- IEEE Program Manager
- Vanessa Lalitte
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- Working Group Chair
- Jayaram Bhasker
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