Standard icon


IEEE Std 1149.10-2017 - IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture

Description: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1™ to describe and operate the on-chip circuits.
  • Status:Active STDHelp

Get This Standard

Buy Purchase a copy of this standardBuyExternal Link
Access with Subscription External Link Standards Online subscribers can access this standard in IEEE Xplore Digital Library. Access Learn More