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IEEE STANDARD

1076.3-1997 - IEEE Standard VHDL Synthesis Packages

Description: The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides a semantics for the VHDL synthesis domain and enables formal verification and simulation acceleration in VHDL-based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the Bit and Boolean types defined in IEEE Std 1076-1993. The numeric types Signed and Unsigned and their associated operators define integer and natural-number arithmetic for arrays of common logic values. Two's-complement and binary encoding techniques are used. The numerical semantics is conveyed by two VHDL packages. This standard also contains any allowable modifications.
  • Status: Superseded Standard Help

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