IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture -Description

Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.

Keywords: boundary-scan, boundary-scan register, circuit boards, circuitry, printed circuit boards, test ports

Content

1. Introduction
- 1.1 Background Reading
- 1.2 An Overview of the Operation of IEEE Std 1149.1
- 1.3 The Use of IEEE Std 1149.1 to Test an Assembled Product
- - 1.3.1 Board Test Goals
  - 1.3.2 What Is Boundary-Scan?
- 1.4 The Use of IEEE Std 1149.1 to Achieve Other Test Goals
2. General Information
- 2.1 Document Outline
- 2.2 Conventions
- 2.3 Definitions
- 2.4 References
3. The Test Access Port (TAP)
- 3.1 Connections That Form the Test Access Port (TAP)
- - 3.1.1 Specifications
  - 3.1.2 Description
- 3.2 The Test Clock Input—TCK
- - 3.2.1 Specifications
  - 3.2.2 Description
- 3.3 The Test Mode Select Input—TMS
- - 3.3.1 Specifications
  - 3.3.2 Description
- 3.4 The Test Data Input—TDI
- - 3.4.1 Specifications
  - 3.4.2 Description
- 3.5 The Test Data Output—TDO
- - 3.5.1 Specifications
  - 3.5.2 Description
- 3.6 The Test Reset Input—TRST*
- - 3.6.1 Specifications
  - 3.6.2 Description
- 3.7 Interconnection of Components Compatible With This Standard
- - 3.7.1 Specifications
  - 3.7.2 Description
- 3.8 Subordination of This Standard Within a Higher Level Test Strategy
- - 3.8.1 Specifications
  - 3.8.2 Description
4. Test Logic Architecture
- 4.1 Test Logic Design
- - 4.1.1 Specifications
  - 4.1.2 Description
- 4.2 Test Logic Realization
- - 4.2.1 Specifications
  - 4.2.2 Description
5. The TAP Controller
- 5.1 TAP Controller State Diagram
- - 5.1.1 Specifications
  - 5.1.2 Description
- 5.2 TAP Controller Operation
- - 5.2.1 Specifications
  - 5.2.2 Description
- 5.3 TAP Controller Initialization
- - 5.3.1 Specifications
  - 5.3.2 Description
6. The Instruction Register
- 6.1 Design and Construction of the Instruction Register
- - 6.1.1 Specifications
  - 6.1.2 Description
- 6.2 Instruction Register Operation
- - 6.2.1 Specifications
  - 6.2.2 Description
7. Instructions
- 7.1 Response of the Test Logic to Instructions
- - 7.1.1 Specifications
  - 7.1.2 Description
- 7.2 Public Instructions
- - 7.2.1 Specifications
  - 7.2.2 Description
- 7.3 Private Instructions
- - 7.3.1 Specifications
  - 7.3.2 Description
- 7.4 The BYPASS Instruction
- - 7.4.1 Specifications
  - 7.4.2 Description
- 7.5 Boundary-Scan Register Instructions
- - 7.5.1 An Overview of the Operation of the Boundary-Scan Register
  - 7.5.2 Specifications for Boundary-Scan Register Instructions
- 7.6 The SAMPLE/PRELOAD Instruction
- - 7.6.1 Specifications
  - 7.6.2 Description
- 7.7 The EXTEST Instruction
- - 7.7.1 Specifications
  - 7.7.2 Description
- 7.8 The INTEST Instruction
- - 7.8.1 Specifications
  - 7.8.2 Description
- 7.9 The RUNBIST Instruction
- - 7.9.1 Specifications
  - 7.9.2 Description
- 7.10 The CLAMP Instruction
- - 7.10.1 Specifications
  - 7.10.2 Description
- 7.11 Device Identification Register Instructions
- 7.12 The IDCODE Instruction
- - 7.12.1 Specifications
  - 7.12.2 Description
- 7.13 The USERCODE Instruction
- - 7.13.1 Specifications
  - 7.13.2 Description
- 7.14 The HIGHZ Instruction
- - 7.14.1 Specifications
  - 7.14.2 Description
8. Test Data Registers
- 8.1 Provision of Test Data Registers
- - 8.1.1 Specifications
  - 8.1.2 Description
- 8.2 Design and Construction of Test Data Registers
- - 8.2.1 Specifications
  - 8.2.2 Description
- 8.3 Test Data Register Operation
- - 8.3.1 Specifications
  - 8.3.2 Description
9. The Bypass Register
- 9.1 Design and Operation of the Bypass Register
- - 9.1.1 Specifications
  - 9.1.2 Description
10. The Boundary-Scan Register
- 10.1 Introduction to This Chapter
- - 10.1.1 Approach
  - 10.1.2 Signal Paths to the On-Chip System Logic
  - 10.1.3 Boundary-Scan Register Cell
- 10.2 Register Design
- - 10.2.1 Specifications
  - 10.2.2 Description
- 10.3 Register Operation
- - 10.3.1 Specifications
  - 10.3.2 Description
- 10.4 General Rules Regarding Cell Provision
- - 10.4.1 Specification
  - 10.4.2 Description
- 10.5 Provision and Operation of Cells at System Logic Inputs
- - 10.5.1 Specifications
  - 10.5.2 Description
- 10.6 Provision and Operation of Cells at System Logic Outputs
- - 10.6.1 Specifications
  - 10.6.2 Description
- 10.7 Bidirectional Signals
- - 10.7.1 Specifications
  - 10.7.2 Description
- 10.8 Redundant Cells
- - 10.8.1 Specifications
  - 10.8.2 Description
- 10.9 Special Cases
- - 10.9.1 Specifications
  - 10.9.2 Description
11. The Device Identification Register
- 11.1 Design and Operation of the Device Identification Register
- - 11.1.1 Specifications
  - 11.1.2 Description
- 11.2 Manufacturer Identity Code
- - 11.2.1 Specifications
  - 11.2.2 Description
- 11.3 Part-Number Code
- - 11.3.1 Specifications
  - 11.3.2 Description
- 11.4 Version Code
- - 11.4.1 Specifications
12. Conformance and Documentation Requirements
- 12.1 Claiming Conformance to This Standard
- - 12.1.1 Specifications
  - 12.1.2 Description
- 12.2 Prime and Second Source Components
- - 12.2.1 Specifications
  - 12.2.2 Description
- 12.3 Documentation Requirements
- - 12.3.1 Specifications
  - 12.3.2 Description
Annex A An Example Implementation Using Level-Sensitive Design Techniques
- A.1 Top-Level Test Logic Design
- A.2 Latch Designs
- A.3 TAP Controller Implementation
- A.4 Instruction Register Implementation
- A.5 Bypass Register Implementation
- A.6 Boundary-Scan Register Implementation

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