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IEEE Std 802.3af™-2003 Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer SpecificationsAmendment: Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI) -Description

Abstract: Support for optionally powering a 10BASE-T, 100BASE-TX or 1000BASE-T DTE device via the Power Interface (PI) using physical layers defined in Clauses 14, 25, and 40. The Power Sourcing Equipment (PSE) is located at an endpoint or midspan, separate from and between the MDIs, and provides power to the Powered Device (PD) over the Link Section. The PSE detection protocol distinguishes a compatible PD from non-compatible devices and precludes the application of power and possible damage to non-compatible devices.The PSE monitors the Maintain Power Signature (MPS) and removes power when it is no longer requested or required.Optional management function requirements are specified.

Keywords: 802.3af, Link Section, midspan, MPS, PD, PI, POE, power, Power over Ethernet, PSE

Content +

  • 1. Introduction
    • 1.4 Definitions
    • 1.5 Abbreviations
    • 14. Twisted-pair medium attachment unit (MAU) and baseband medium, type 10BASE-T
    • 22. Reconciliation Sublayer (RS) and Media Independent Interface (MII)
      • 22.2.4 Management functions
    • 30. 10 Mb/s, 100 Mb/s, 1000 Mb/s and 10 Gb/s Management
    • 30.1 Overview
      • 30.1.1 Scope
      • 30.1.2 Relationship to zobjects in IEEE 802.1F
      • 30.1.4 Management model
      • 30.2.3 Containment
      • 30.2.5 Capabilities
    • 30.9 Management for Power Sourcing Equipment (PSE)
      • 30.9.1 PSE managed object class
    • 30.10 Layer management for Midspan
      • 30.10.1 Midspan managed object class
      • 30.10.2 PSE Group managed object class
    • 40. Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer and baseband medium, type 1000BASE-T
      • 40.12.2 Major capabilities/options
      • 40.12.7 PMA Electrical Specifications
    • 33. Data Terminal Equipment (DTE) Power via Media Dependent Interface (MDI)
    • 33.1 Overview
      • 33.1.1 Objectives
      • 33.1.2 Compatibility considerations
      • 33.1.3 Relationship of Power via MDI to the IEEE 802.3 Architecture
    • 33.2 Power sourcing equipment
      • 33.2.1 PSE location
      • 33.2.2 PI pin assignments
      • 33.2.3 PSE state diagrams
      • 33.2.4 PD detection
      • 33.2.5 PSE validation circuit
      • 33.2.6 PSE detection of PDs
      • 33.2.7 PSE classification of PDs
      • 33.2.8 Power supply output
      • 33.2.9 Power supply allocation
      • 33.2.10 PSE power removal
    • 33.3 Powered devices
      • 33.3.1 PD PI
      • 33.3.2 PD state diagram
      • 33.3.3 PD valid and non-valid detection signatures
      • 33.3.4 PD classifications
      • 33.3.5 PD power
      • 33.3.6 PD Maintain Power Signature
    • 33.4 Additional Electrical specifications
      • 33.4.1 Isolation
      • 33.4.2 Fault tolerance
      • 33.4.3 Impedance balance
      • 33.4.4 Common-mode output voltage
      • 33.4.5 Pair-to-pair output noise voltage
      • 33.4.6 Differential noise voltage
      • 33.4.7 Return loss
      • 33.4.8 Midspan PSE device additional requirements
    • 33.5 Environmental
      • 33.5.1 General safety
      • 33.5.2 Network safety
      • 33.5.3 Installation and maintenance guidelines
      • 33.5.4 Patch panel considerations
      • 33.5.5 Cabling resistance unbalance
      • 33.5.6 Telephony voltages
      • 33.5.7 Electromagnetic emissions
      • 33.5.8 Temperature and humidity
      • 33.5.9 Labeling
    • 33.6 Management function requirements
      • 33.6.1 PSE registers
    • 33.7 Protocol Implementation Conformance Statement (PICS) proforma for Clause 33, DTE Power via MDI
      • 33.7.1 Introduction
      • 33.7.2 Identification
      • 33.7.3 PICS proforma tables for DTE Power via MDI
  • Annex 30A GDMO specification for IEEE 802.3 managed object classes
    • 30A.10.1 ResourceTypeID, formal definition
    • 30A.16 PSE managed object class
      • 30A.16.1 PSE, formal definition
      • 30A.16.2 PSE attributes
      • 30A.16.3 PSE actions
    • 30A.17 Midspan managed object class
      • 30A.17.1 Midspan attributes
      • 30A.17.2 Midspan notifications
    • 30A.18 PSE Group managed object class
      • 30A.18.1 PSE Group attributes
      • 30A.18.2 PSE Group notifications
  • Annex 30B GDMO and ASN.1 definitions for management
    • 30B.2 ASN.1 module for CSMA/CD managed objects
  • Annex 33A PSE Detection of PDs
  • Annex 33B Cabling guidelines
  • Annex 33C Recommended test configurations and procedures
    • 33C.1 Recommended PSE output test procedures
      • 33C.1.1 Test Procedure PSE-1 (output polarity, output voltage, and continuous output power)
      • 33C.1.2 Test Procedure PSE-2 (load regulation)
      • 33C.1.3 Test Procedure PSE-3 (ripple and noise)
      • 33C.1.4 Test Procedure PSE-4 (output current in startup mode)
      • 33C.1.5 Test Procedure PSE-5 (IDLE state current)
      • 33C.1.6 Test Procedure PSE-6 (overload current detection range and overload timings)
      • 33C.1.7 Test Procedure PSE-7 (short circuit current and timing)
      • 33C.1.8 Test Procedure PSE-8 (turn on rise time)
      • 33C.1.9 Test Procedure PSE-9 (turn off time)
      • 33C.1.10 Test Procedure PSE-10 (turn on, detection and classification time)
      • 33C.1.11 Test Procedure PSE-11 (detection backoff time)
      • 33C.1.12 Test Procedure PSE-12 (port capacitance during detection)
    • 33C.2 Recommended PSE AC disconnect-detection test procedures
      • 33C.2.1 Test Procedure PSE-13 (ac disconnect pulse parameters)
      • 33C.2.2 Test Procedure PSE-14 (port impedance)
    • 33C.3 Recommended PSE detection signature test procedures
      • 33C.3.1 Test Procedure PSE-15 (signature detection parameters)
    • 33C.4 Recommended PD detection signature test procedures
      • 33C.4.1 Test Procedure SIG-1 (PD signature characteristics)
    • 33C.5 Recommended PD power supply test procedures
      • 33C.5.1 Test Procedure PD-1 (all parameters)
  • Annex 33D PSE-PD stability
    • 33D.1 Recommended PSE design guidelines and test setup
    • 33D.2 Recommended PD design guidelines
  • Annex 33E Cabling resistance unbalance

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